Semiconductor methods for manufacturing integrated circuits require that the surface density of each layer be within a given range and that its distribution be as homogeneous as possible in each of the constituent layers of the multilayer integrated circuit. The conventional method for manufacturing integrated circuits relies on the superposition of successive layers through successive maskings of silicon slices, and on photo etching, scattering, metallizing, polishing, and doping operations, etc. The superposition of the various layers of the integrated circuit makes it possible to implement elementary logic functions. The physical design of the elements constituting an integrated circuit introduces surface variations throughout the circuit. The introduction of so-called dummy surfaces between the constituent elements of the physical design of the integrated circuit is therefore necessary in order to homogenize the surface density of a given layer of the integrated circuit and allow the layer above it to be produced. These surfaces are called “dummy” surfaces because they are not involved in any of the elements of the integrated circuit. They are also known as “filler” structures. In order to allow designers to comply with the surface density rules imposed, the manufacturer generally defines the shape and maximum sizes of the dummy surfaces that must be inserted, as well as the maximum spacing between dummy surfaces and the exclusion areas of the dummy surfaces, which correspond to the space around the elements of the physical design in which no surface should be present.
There are methods known in the prior art for inserting dummy surfaces, which implement the integrated circuit globally, defining a pattern and inserting it into the empty spaces of the integrated circuit. In general, squares or rectangles are inserted into the empty spaces with a spacing optimized so as to conform to the required surface density of the circuit. These methods make it possible to homogenize the surface density without requiring any change in the arrangement of the physical design of the circuit. However, this solution has several disadvantages. With this type of method, dummy surfaces are inserted even in regions where the density is already acceptable, and thus in certain regions the density can exceed the maximum density accepted by the manufacturer, making it necessary to modify the implementation performed. Sometimes the required minimum density cannot be achieved because the physical design is such that it is impossible to insert dummy surfaces. In this case, the design being completely finished, no local modification is possible and the entire design must be revised. Moreover, the performance of the circuit cannot be controlled with this type of method, and the deterioration in the performance of the integrated circuit produced by the dummy surfaces can be too great. Furthermore, the addition of a large number of elements generates design files for the integrated circuit that are too large. Lastly, these methods require too long a development time in order to find the pattern that will produce the best result. The last two drawbacks mentioned grow even more serious as the number of layers used and the size of the circuit increase.
Manufacturers generally supply a design rules control (DRC) tool that allows designers to verify whether their integrated circuits comply with the requisite design and density rules. This tool performs a surface density check on each of the layers of the integrated circuit, by means of a calculation of the surface density in density control windows whose shapes and dimensions are optimized by the manufacturers.
The design of complex integrated circuits with large numbers of transistors is implemented hierarchically. The circuit is divided into interconnected units, each unit being divided into blocks, also interconnected. The physical design of the blocks can be implemented according to two different methods. The first, known as the “standard cell” method, consists of assembling and interconnecting cells from a predefined cell library, in which each cell corresponds to a logic gate. The blocks thus created are composed of an array of several cells placed in rows and generally interconnected by channels located between the rows. The second, known as the custom cell method, consists of designing cells that are specially sized based on the electrical characteristics implemented. The interconnections of cells of this type are produced inside the cell itself. The blocks obtained by combining cells of this type are thus generally more complex, and therefore require a more complex operation for the insertion of dummy surfaces into the various layers of the circuit.
The interconnections between the blocks that form the units and the interconnections between the units that form the physical design of a circuit are implement by means of a specific automatic routing system. The various methods can use different design rules, but all of them must respect the limits imposed by the manufacturer. It would therefore be desirable to have a method that is selective as to the design method used, and that conforms to the manufacturers' rules. Moreover, the known methods of the prior art do not generally respect the hierarchy resulting from the physical design, and require an integral implementation of the design each time one of its blocks is modified. A method that is selective as to the manufacturing method and that respects the hierarchy of the design would make it possible to selectively implement only the modified block, applying only the method used for the design of the block in question, and would make it possible to reuse the various blocks or units, with their optimized dummy surfaces, in other integrated circuits.
Another problem in the design of integrated circuits, the magnitude of which increases as the critical dimensions decrease, is coupling between nearby metal links running through the layer or between those that pass over each other because they run through different metal levels. One way to improve the performance of the circuit is to define design rules for the metal links with spacings larger than the minimum allowed by the technology, which would reduce nearby coupling phenomena. The maximum filler density of the design under these conditions is less than or equal to the minimum density accepted by the manufacturer. But the addition of dummy surfaces will then be necessary, and they will contribute to the coupling with the metal links. The insertion of dummy surfaces around the metal routing links of the circuits is therefore an important stage for the performance of the integrated circuit.
There are known methods in the prior art for filling the empty spaces of an integrated circuit using a “reverse mask” method. The negatives of the masks used for the physical design are used to protect the constituent elements of the circuit and to expose the empty spaces, which are then filled homogeneously. This method entails an enormous additional cost and too great a risk of defects because of the coupling problems due to the proximity of the dummy surfaces and the constituent elements of the circuit.
All integrated circuit design methods must respect the surface density rules required by manufacturers and the various constraints imposed by coupling problems in the circuits. The number of added elements should be as low as possible, and the methods should avoid, insofar as possible, any coupling between the metal links and the added surfaces, while respecting the exclusion areas. Designers, in order to optimize the performance of their circuits, will also choose to avoid the superposition of dummy surfaces with metal links running through another level but with the same orientation. In this context, it is advantageous to define a mode for inserting dummy surfaces that can accommodate various design methods, their hierarchies, and the constraints imposed by manufacturers and designers. One way to facilitate the implementation would be to use the density control windows specified by the manufacturers. The surface density calculated would make it possible to selectively insert dummy surfaces into only the low-density areas. The dummy surfaces must be inserted so as to respect the exclusion areas and a maximum spacing between dummy surfaces.